The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory for discretely storing an analog signal such as an image signal in the form of an analog value.
In a nonvolatile semiconductor memory that discretely stores an analog signal such as an image signal in the form of an analog value, as the memory capacity increases, the number of memory cells for individually storing the analog values and the number of interconnections increase, and the pattern size on the memory chip decreases more and more.
As these factors that produce a defect in the memory chip increase, it is important to remedy the defect occurred in the manufacturing process in order to increase the productivity and to reduce the cost.
Currently, in an imaging device such as a digital still camera, an analog image signal obtained by an image sensing element such as a CCD is converted into digital data by an A/D converter, and is stored as a digital value in a nonvolatile semiconductor memory such as a flash memory.
In such a digital nonvolatile semiconductor memory, in order to remedy a memory cell defect having occurred in the manufacturing process, a redundant cell is formed on the pattern in advance, and a defective memory cell is replaced with the redundant cell when necessary.
FIG. 20 shows a redundant arrangement of a conventional semiconductor memory.
Referring to FIG. 20, redundant cells 205 replaces all memory cells belonging to a predetermined column or row of a memory cell array 204.
Defective cell addresses R0 to Rn indicating the position of a defective memory cell in accordance with the defect inspection result of a memory cell array are set in a redundant address setting unit 201.
The defective cell addresses R0 to Rn are compared with cell select addresses A0 to An by a redundant address comparator 202.
A redundancy indicating signal (ON/OFF) indicating whether this redundant arrangement is to be operated or not is set in the redundant address setting unit 201.
When the redundancy indicating signal is ON and the redundant address comparator 202 determines that the defective cell addresses R0 to Rn and the cell select addresses A0 to An coincide with each other, an output from a NAND gate 206 changes to LOW level to turn off all gates 207.
In contrast to this, an output from an AND gate 208 changes to HIGH level to turn on a gate 209.
Accordingly, supply of all column select signals 210 decoded by an address decoder 203 is stopped in response to the OFF state of the gates 207, and a column select signal 211 is supplied to the redundant cell 205 in response to the ON state of the gate 209. The redundant cell 205 is selected in place of a predetermined column of the memory cell array 204 to write/read out data.
FIGS. 21A and 21B show arrangements of the redundant address setting unit 201. In a laser fuse scheme redundant address setting unit, as shown in FIG. 21A, during the chip manufacture, the fuse is disconnected by a laser beam in accordance with the inspection result of the memory cell array 204, to set the defective cell addresses R0 to Rn and to turn on/off the redundancy indication signal. In a flash memory scheme redundant address setting unit, as shown in FIG. 21B, a redundant address is stored in the nonvolatile memory cell.
In these conventional semiconductor memories, however, a redundant arrangement which becomes unnecessary when no memory cell has a defect, i.e., a redundant cell and a control circuit portion for it, must be formed on the chip in advance. Hence, the chip area cannot accordingly be utilized effectively.
In particular, in an analog nonvolatile semiconductor memory which stores an analog signal in the form of an analog value, the presence of a redundant arrangement is a more serious issue partly because the peripheral circuit concerning write/read out operation is larger than in a digital memory.
In the conventional redundant arrangement, for example, for a memory block size of 512 columnsxc3x974,096 rows (2 Mbits), redundant cells for only 2 columnsxc3x971 row are provided. In this case, in spite that the number of all redundant cells is 512xc3x972+4,096=5,120, concerning a defective cell at a random position which occurs very often as a defect mode, only 3 defective cells can be reliably remedied, and such defective cells cannot be efficiently coped with.
A large number of redundant cells may be provided so that they can replace more columns or rows. In this case, however, the chip area occupied by the redundant arrangement increases greatly.
With this redundant arrangement, although an error in digital information can be corrected by using a check sum or the like, an error in analog information cannot be corrected easily. Since one memory cell stores analog information corresponding to a large number of bits, analog information stored in one memory cell is much more important than digital information stored in one memory cell. Therefore, a defective cell must be remedied reliably.
According to the present invention, there is provided a nonvolatile semiconductor memory comprising a memory unit having a plurality of memory cells to discretely store an analog signal, such as an image signal, as analog data in the form of an analog value, a memory control unit for sequentially selecting the memory cells as a read out target of the memory unit in response to a predetermined clock, a defect position detection unit for detecting, on the basis of defect position information indicating a position of defective analog data included in the analog data read out from the memory unit, whether a memory cell corresponding to the defect position is selected by the memory control unit, and outputting a detection output, and a data correction unit for correcting the analog data at the defect position in accordance with the detection output from the defect position detection unit by using another analog data of the analog signal stored in said memory unit.